Non-volatile semiconductor memory cells permitting charge storage capability are well known in the art. The charges stored thereon define the states of a memory cell. Typically, the states can be either two levels or more than two levels (for multi-level states storage). In terms of charge storage scheme, in general, the memory cells can be divided into two main categories. The first type of memory uses a conductive or semiconductor region for charge storage. The charge storage region is electrically insulated from but capacitively coupled to surrounding electrodes through surrounding insulators. Charges stored in such memory are evenly distributed through out the storage region. Memory cells with such type of charge storage scheme are commonly referred as “floating-gate” type of cells. Typically, such floating gate memory cells have been of the single-gate type, split-gate type, or stack-gate type, or a combination thereof.
The second type of memory stores charges in a plurality of discrete storage sites, such as trapping centers of an appropriate dielectric material (“trapping dielectric”). The storage sites in the trapping dielectric is electrically insulated from but capacitively coupled to surrounding electrodes through a storage insulator. The Memory cells employing such type of storage scheme are commonly referred as “charge-trapping” memory cells. The storage sites can be also in nano-crystal form, which is typically a semiconductor in nanometer scale (nano-crystals). The memory cells employing such type of storage scheme are commonly referred as “nano-crystal” memory cells. These memory cells do not require a floating-gate. Therefore, it provides advantages over the floating-gate memory cells in area such as negligible interference between adjacent cells, and reduced process complexity. Furthermore, the charges in such memory cell can be stored at localized sites (traps or nano-crystals). Therefore it also has the advantage that in the event there is a local breakdown in region of the storage dielectric or in surrounding dielectrics next to one of the storage sites, charges stored at other sites can still be retained.
Stack-gate memory has the advantages over other types of memory cells on a simpler process in manufacturing such type of memory cell. One of such non-volatile memory cells has been proposed in U.S. Pat. No. 5,877,524, and in U.S. Pat. No. 6,172,397 B1, which are hereby incorporated by reference. As will be described hereinafter, there are several disadvantages in the disclosures of prior art. The present invention provides cell structures and operation method with advantages over the prior art.
The present invention can best be understood with an understanding of how the memory cells in prior art are constructed and how they are operated for program and erase operations. Thus a short introduction is presented to describe the prior art cell structure, and the cell operations.
U.S. Pat. Nos. 5,877,524, and 6,172,397 B1 taught memory cell structure and operation method (e.g. program and erase). A relevant technical article “Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a p-channel Cell”, by T. Ohnakado et al., IEDM Technical Digest, pp. 279–282, 1995, described in detail the operation and the performance of memory cell taught in U.S. Pat. Nos. 5,877,524, and 6,172,397 B1. The memory cell is a p-channel based cell having advantage on higher injection efficiency (about 10 to 100 times higher) than an n-channel based cell (e.g. cell in U.S. Pat. No. 5,106,772). Here, the term “injection efficiency” is defined as the ratio of the number of carriers entering into FG to the number of charges supplied.
Illustrated in FIG. 1A is the bias condition for program operation along with a cross sectional view for a cell structure 100 of the prior art. The cell 100 comprises a storage transistor having a control gate (CG) 12, a floating gate (FG) 14, a body 16, a source 18, and a drain 20 with a channel 22 of the body 16 defined therebetween. Both the source 18 and the drain 20 are of p-type conductivity. The body 16 is of n-type conductivity and is in a well 24 of same conductivity (“n-Well”). The FG 14 is disposed over and insulated from the channel 22 by a layer of storage insulator 26. Likewise, the CG 12 is disposed over and insulated from the FG 14 by a coupling insulator 28. The prior art cell 100 can be electrically programmed by using BBHE injection mechanism. Referring to FIG. 1A, there are shown electrons 30 generated in the drain 20 under drain-to-FG overlapping region 31 through Band-to-Band Tunneling (“BTBT”). The generated electrons 30 are accelerated in an adjacent lateral field to get heated up. The transport direction of a portion of those electrons can be redirect to the FG after experiencing scattering event and portion of them can climb over barrier height between the n-Well 24 and the storage insulator 26 to enter into FG 14, as illustrated in the dotted-line arrow 32 in FIG. 1A. Also illustrated are hole carriers (holes) 34 generated through BTBT in the drain 20 under the overlapping region 31. Due to the bias polarity, the holes 34 are swept away by electric field in that region along the path shown in dash-line arrow 36 and subsequently move out of the drain 20. The holes 34 thus have no effect on the charges stored on FG 14. The source 18, drain 20, CG, 12, and n-Well 24 are attached to their respective electrodes, through which biases are applied thereto. Typical voltages for programming the memory cell are: +10V (applied to CG 12), −6V (applied to drain 20), and 0V (applied to the n-Well 24). The source 18 is left open during the program operation.
FIG. 1B illustrates the bias condition for an erase operation of the prior art cell 100. The erase operation in prior art is done by utilizing Fowler-Nordheim tunneling to remove electrons 37 stored in FG 14 along the trajectory shown in dotted-lines 38a and 38b. Typical voltages for erasing the memory cell are: −10V (applied to CG 12), +10V (applied to source 18), and +10V (applied to the n-Well 24). The drain 20 is left open during the erase operation.
As described hereinbefore, the memory cells in U.S. Pat. No. 5,877,524, and in U.S. Pat. No. 6,172,397 B1 are erased by Fowler-Nordheim tunneling mechanism. Same mechanism has been widely employed in other types of memory cells (for example, U.S. application Ser. No. 10/178,658, and U.S. Pat. Nos. 4,957,877, 5,106,772, 5,146,426, and 5,432,739). In erasing these types of nonvolatile memories with such mechanism, a large voltage drop (typically ranging from 10 to 20V) across the storage insulator is required to perform the operation in order to set a desired logic states (e.g. a “0” state) to the memory. Employing Fowler-Nordheim tunneling mechanism to erase these types of memory cells unavoidably introduces stress field in the range of about 10 MV/cm to the storage insulator, which isolates the floating gate or the storage sites from surrounding conductive regions. This high field stress effect on the storage insulator results in charge leakage and retention failure even when memory cells are under a low field condition. This effect is known as the Stress Induced Leakage Current (SILC), and has been shown being the dominant leakage mechanism causing retention failure in non-volatile memory industry (see K. Naruke et al, “Stress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thickness”, IEDM Technical Digest, pp. 424–427, 1988.). Therefore, the memory cell disclosed in prior art is believed suffered from high field induced SILC issue.
Like other types of stack-gate memory cell, the cell of prior art is compact in size as it contains only a storage transistor. However, an additional disadvantage associated with this type of memory cell is that the BBHE program scheme can often introduce cell disturb problem in memory cells sharing a same drain junction. Therefore, this restricts the drain junction of each memory cell from being shared with neighboring memory cells when cell is arranged in a memory array. The viable array architecture taught therein requires a metal contact to be formed in a pair of cells. Further, for disturb prevention, a select transistor is often required to be disposed in between and connected in series with the storage transistor and the contact. The cell size thus can be undesirably enlarged. Therefore, such cell thus is believed to have the disadvantage on larger cell size.
The present invention provides cell structure and operation method of a p-channel based electrical erasable programmable memory cell that can avoid the high field stress effect and the cell disturb problem. The erase operation of the present cell permits the voltage drop across the storage insulator be confined in range less than about 3 MV/cm. Therefore, it avoids the high field stress on the insulator and hence the SILC issue. Other advantages, objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.